Memory system and operating method of the same

ABSTRACT

A memory system includes: a memory device that includes a plurality of memory blocks each of which includes a plurality of pages that store data; and a controller suitable for performing command operations corresponding to a plurality of commands received from a host on the plurality of memory blocks, applying pass voltages to a dummy region of the memory device when the command operations are performed, detecting first parameters for the plurality of memory blocks based on the applied pass voltages, and copying and storing data stored in first memory blocks in second memory blocks among the plurality of memory blocks based on the first parameters.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application claims priority of Korean Patent Application No.10-2017-0129791, filed on Oct. 11, 2017, which is incorporated herein byreference in its entirety.

BACKGROUND 1. Field

Various embodiments of the present invention generally relate to amemory system. Particularly, the embodiments relate to a memory systemcapable of processing data with a memory device, and an operating methodof the memory system.

2. Description of the Related Art

The emerging computer environment paradigm is ubiquitous computing, thatis, computing systems that can be used anytime and anywhere. As aresult, use of portable electronic devices such as mobile phones,digital cameras, and notebook computers has rapidly increased. Theseportable electronic devices generally use a memory system having one ormore memory devices for storing data. A memory system in such device maybe used as a main memory device or an auxiliary memory device.

Memory systems provide excellent stability, durability, high informationaccess speed, and low power consumption since they have no moving parts.Examples of memory systems having such advantages include universalserial bus (USB) memory devices, memory cards having various interfaces,and solid state drives (SSD).

SUMMARY

Embodiments of the present invention are directed to a memory systemcapable of processing data with a memory device quickly and stably byminimizing the complexity and performance deterioration of the memorysystem and maximizing the utility efficiency of the memory device, andan operating method of the memory system.

In accordance with an embodiment of the present invention, a memorysystem includes: a memory device that includes a plurality of memoryblocks each of which includes a plurality of pages that store data; anda controller suitable for performing command operations corresponding toa plurality of commands received from a host on the plurality of memoryblocks, applying pass voltages to a dummy region of the memory devicewhen the command operations are performed, detecting first parametersfor the plurality of memory blocks based on the applied pass voltages,and copying and storing data stored in first memory blocks in secondmemory blocks among the plurality of memory blocks based on the firstparameters.

The dummy region may include a dummy word line or a dummy page which isset in each of the memory blocks, and wherein the controller may applythe pass voltages to each dummy word line or dummy page.

The pass voltages may have a maximum level that is set based on voltagelevels applied to each of the plurality of memory blocks when thecommand operations are performed.

The first parameters may be voltage offsets or voltage distributionoffsets corresponding to the pass voltages applied to the dummy wordline or the dummy page of each of the plurality of memory blocks.

The controller may detect second parameters for each of the plurality ofmemory blocks corresponding to performance of the command operations.

The second parameters may be command operation counts corresponding tothe performance of the command operations in each of the plurality ofmemory blocks.

The controller may adjust the second parameters, and subsequently selectthe first memory blocks in accordance with the adjusted secondparameters.

The dummy word line in each of the plurality of memory blocks may be setas a region having a first bit in a first word line or to a word lineprevious to the first word line, among a plurality of word lines in eachof the plurality of memory blocks.

The dummy page in each of the plurality of memory blocks may be set as aregion having a first bit in a first page or to a page previous to thefirst page, among a plurality of pages included in each of the pluralityof memory blocks.

The dummy region includes a group of a plurality of word lines or aplurality of pages in each of the plurality of memory blocks, andwherein the controller may apply the pass voltages to each group.

In accordance with an embodiment of the present invention, an operatingmethod of a memory system includes: receiving a plurality of commandsfrom a host for a memory device that includes a plurality of memoryblocks each of which includes a plurality of pages that store data;performing command operations corresponding to the commands on theplurality of memory blocks; applying pass voltages to a dummy region ofthe memory device when the command operations are performed; detectingfirst parameters for the plurality of memory blocks based on the appliedpass voltages; and copying and storing data stored in first memoryblocks in second memory blocks among the plurality of memory blocksbased on the first parameters.

The dummy region may include a dummy word line or a dummy page which isset in each of the plurality of memory blocks, and wherein the applyingoperation may comprise applying the pass voltages to each dummy wordline or dummy page.

The pass voltages may have a maximum level that is set based on voltagelevels applied to each of the plurality of memory blocks when thecommand operations are performed.

The first parameters may be voltage offsets or voltage distributionoffsets corresponding to the pass voltages applied to the dummy wordline or the dummy page of each of the plurality of memory blocks.

The operating method may further include: detecting second parametersfor each of the plurality of memory blocks corresponding to performanceof the command operations.

The second parameters may be command operation counts corresponding tothe performance of the command operations in each of the plurality ofmemory blocks.

The storing of the data stored in first memory blocks in second memoryblocks may include: adjusting the second parameters; and selecting thefirst memory blocks in accordance with the adjusted second parameters.

The dummy word line each of the plurality of memory blocs may be set asa region having a first bit in a first word line or to a word lineprevious to the first word line, among a plurality of word linesincluded in each of the plurality of memory blocks.

The dummy page in each of the plurality of memory blocks may be set as aregion having a first bit in a first page or to a page previous to thefirst page, among a plurality of pages in each of the plurality ofmemory blocks.

The dummy region includes a group of a plurality of word lines or aplurality of pages in each of the plurality of memory blocks and whereinthe applying operation comprises applying the pass voltages to eachgroup.

In accordance with an embodiment of the present invention, a memorysystem includes: a memory device including a plurality of memory blocks,each having a dummy region; and a controller suitable for detecting readdisturbances of the plurality of memory blocks by applying a passvoltage to the dummy regions after a read operation, and controlling thememory device to perform a read reclaim operation according to the readdisturbances.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a data processing system inaccordance with an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating an exemplary configuration ofa memory device employed in a memory system of FIG. 1.

FIG. 3 is a circuit diagram illustrating an exemplary configuration of amemory cell array of a memory block in a memory device shown in FIG. 1.

FIG. 4 is a schematic diagram illustrating an exemplarythree-dimensional (3D) structure of the memory device of FIG. 2.

FIGS. 5 to 7 illustrate an example of a data processing operation when aplurality of command operations corresponding to a plurality of commandsare performed in a memory system in accordance with an embodiment of thepresent invention

FIG. 8 is a flowchart describing an operation of processing data in thememory system in accordance with an embodiment of the present invention.

FIGS. 9 to 17 are diagrams schematically illustrating applicationexamples of the data processing system in accordance with variousembodiments of the present invention.

DETAILED DESCRIPTION

Various embodiments of the present invention are described below in moredetail with reference to the accompanying drawings. However, variouselements and features of the present invention may be configured orarranged differently than shown in the described embodiments, as will beapparent to those skilled in the art in light of this disclosure. Thus,the present invention is not limited to the embodiments set forthherein. Rather, the described embodiments are provided so that thisdisclosure is thorough and complete and fully conveys the presentinvention to those skilled in the art to which this invention pertains.Moreover, reference to “an embodiment” does not necessarily mean onlyone embodiment, and different references to “an embodiment” are notnecessarily to the same embodiment(s). Throughout the disclosure, likereference numerals refer to like parts throughout the various figuresand embodiments of the present invention.

It will be understood that, although the terms “first”, “second”,“third”, and so on may be used herein to identify various elements,these elements are not limited by these terms. These terms are used todistinguish one element from another element. Thus, a first elementdescribed below could also be termed as a second or third elementwithout departing from the spirit and scope of the present invention.

The drawings are not necessarily to scale and, in some instances,proportions may have been exaggerated in order to clearly illustratevarious features of the disclosed embodiments.

It will be further understood that when an element is referred to asbeing “connected to”, or “coupled to” another element, it may bedirectly on, connected to, or coupled to the other element, or one ormore intervening elements may be present. In addition, it will also beunderstood that when an element is referred to as being “between” twoelements, it may be the only element between the two elements, or one ormore intervening elements may also be present.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to limit the present invention. Asused herein, singular forms are intended to include the plural forms andvice versa, unless the context clearly indicates otherwise. It will befurther understood that the terms “comprises,” “comprising,” “includes,”and “including” when used in this specification, specify the presence ofthe stated elements and do not preclude the presence or addition of oneor more other elements. As used herein, the term “and/or” includes anyand all combinations of one or more of the associated listed items.

Unless otherwise defined, all terms including technical and scientificterms used herein have the same meaning as commonly understood by one ofordinary skill in the art to which the present invention pertains inview of the present disclosure. It will be further understood thatterms, such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe context of the present disclosure and the relevant art and not beinterpreted in an idealized or overly formal sense unless expressly sodefined herein.

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Thepresent invention may be practiced without some or all of these specificdetails. In other instances, well-known process structures and/orprocesses have not been described in detail in order not tounnecessarily obscure the present invention.

It is also noted, that in some instances, as would be apparent to thoseskilled in the relevant art, a feature or element described inconnection with one embodiment may be used singly or in combination withother features or elements of another embodiment, unless otherwisespecifically indicated.

Various embodiments of the present invention will be described in detailwith reference to the attached drawings.

FIG. 1 is a block diagram illustrating a data processing system 100 inaccordance with an embodiment of the present invention.

Referring to FIG. 1, the data processing system 100 may include a host102 operatively coupled to a memory system 110.

The host 102 may include any of various portable electronic devices suchas a mobile phone, MP3 player and laptop computer, or any of variousnon-portable electronic devices such as a desktop computer, gamemachine, TV, and projector.

The host 102 may include at least one operating system (OS), which maymanage and control overall functions and operations of the host 102, andprovide operation between the host 102 and a user using the dataprocessing system 100 or the memory system 110. The OS may supportfunctions and operations corresponding to the use purpose and usage of auser. For example, the OS may be divided into a general OS and a mobileOS, depending on the mobility of the host 102. The general OS may bedivided into a personal OS and an enterprise OS, depending on theenvironment of a user. For example, the personal OS configured tosupport a function of providing a service to general users may includeWindows and Chrome, and the enterprise OS configured to secure andsupport high performance may include Windows server, Linux and Unix.Furthermore, the mobile OS configured to support a function of providinga mobile service to users and a power saving function of a system mayinclude Android, iOS and Windows Mobile. The host 102 may include aplurality of OSs, and execute an OS to perform an operationcorresponding to a user's request on the memory system 110.

The memory system 110 may operate to store data for the host 102 inresponse to a request of the host 102. Non-limiting examples of thememory system 110 may include a solid state drive (SSD), a multi-mediacard (MMC), a secure digital (SD) card, a universal storage bus (USB)device, a universal flash storage (UFS) device, compact flash (CF) card,a smart media card (SMC), a personal computer memory card internationalassociation (PCMCIA) card and memory stick. The MMC may include anembedded MMC (eMMC), reduced size MMC (RS-MMC) and micro-MMC, and the.The SD card may include a mini-SD card and micro-SD card.

The memory system 110 may be embodied by various types of storagedevices. Examples of such storage devices may include, but are notlimited to, volatile memory devices such as a DRAM dynamic random accessmemory (DRAM) and a static RAM (SRAM) and nonvolatile memory devicessuch as a read only memory (ROM), a mask ROM (MROM), a programmable ROM(PROM), an erasable programmable ROM (EPROM), an electrically erasableprogrammable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-changeRAM (PRAM), a magneto-resistive RAM (MRAM), resistive RAM (RRAM) and aflash memory. The flash memory may have a 3-dimensional (3D) stackstructure.

The memory system 110 may include a memory device 150 and a controller130. The memory device 150 may store data for the host 102, and thecontroller 130 may control data storage into the memory device 150.

The controller 130 and the memory device 150 may be integrated into asingle semiconductor device, which may be included in the various typesof memory systems as exemplified above. For example, the controller 130and the memory device 150 may be integrated as one semiconductor deviceto constitute an SSD. When the memory system 110 is used as an SSD, theoperating speed of the host 102 connected to the memory system 110 canbe improved. In addition, the controller 130 and the memory device 150may be integrated as one semiconductor device to constitute a memorycard. For example, the controller 130 and the memory device 150 mayconstitute a memory card such as a PCMCIA (personal computer memory cardinternational association) card, CF card, SMC (smart media card), memorystick, MMC including RS-MMC and micro-MMC, SD card including mini-SD,micro-SD and SDHC, or UFS device.

Non-limiting application examples of the memory system 110 may include acomputer, an Ultra Mobile PC (UMPC), a workstation, a net-book, aPersonal Digital Assistant (PDA), a portable computer, a web tablet, atablet computer, a wireless phone, a mobile phone, a smart phone, ane-book, a Portable Multimedia Player (PMP), a portable game machine, anavigation system, a black box, a digital camera, a Digital MultimediaBroadcasting (DMB) player, a 3-dimensional television, a smarttelevision, a digital audio recorder, a digital audio player, a digitalpicture recorder, a digital picture player, a digital video recorder, adigital video player, a storage device constituting a data center, adevice capable of transmitting/receiving information in a wirelessenvironment, one of various electronic devices constituting a homenetwork, one of various electronic devices constituting a computernetwork, one of various electronic devices constituting a telematicsnetwork, a Radio Frequency Identification (RFID) device, or one ofvarious components constituting a computing system.

The memory device 150 may be a nonvolatile memory device and may retaindata stored therein even though power is not supplied. The memory device150 may store data provided from the host 102 through a write operation,and provide data stored therein to the host 102 through a readoperation. The memory device 150 may include a plurality of memoryblocks 152, 154, 156 . . . (hereinafter, referred to as “memory blocks152 to 156”) each of which may include a plurality of pages, and each ofthe pages may include a plurality of memory cells coupled to a wordline. In an embodiment, the memory device 150 may be a flash memory. Theflash memory may have a 3-dimensional (3D) stack structure.

Since the structure of the memory device 150 including its 3D stackstructure will be described in detail later with reference to FIGS. 2 to4, and the memory device 150 including a plurality of memory dies, eachof which includes a plurality of planes, each of which includes aplurality of memory blocks 152 to 156 will be described in detail laterwith reference to FIG. 6, further description of these elements andfeatures are omitted here.

The controller 130 may control the memory device 150 in response to arequest from the host 102. For example, the controller 130 may providedata read from the memory device 150 to the host 102, and store dataprovided from the host 102 into the memory device 150. For thisoperation, the controller 130 may control read, write, program and eraseoperations of the memory device 150.

The controller 130 may include a host interface (I/F) 132, a processor134, an error correction code (ECC) component 138, a Power ManagementUnit (PMU) 140, a memory I/F 142 such as a NAND flash controller (NFC),and a memory 144 all operatively coupled via an internal bus.

The host interface 132 may be configured to process a command and dataof the host 102, and may communicate with the host 102 through one ormore of various interface protocols such as universal serial bus (USB),multi-media card (MMC), peripheral component interconnect-express(PCI-E), small computer system interface (SCSI), serial-attached SCSI(SAS), serial advanced technology attachment (SATA), parallel advancedtechnology attachment (PATA), enhanced small disk interface (ESDI) andintegrated drive electronics (IDE).

The ECC component 138 may detect and correct an error contained in thedata read from the memory device 150. In other words, the ECC component138 may perform an error correction decoding process to the data readfrom the memory device 150 through an ECC code used during an ECCencoding process. According to a result of the error correction decodingprocess, the ECC component 138 may output a signal, for example, anerror correction success/fail signal. When the number of error bits ismore than a threshold value of correctable error bits, the ECC component138 may not correct the error bits, and may output an error correctionfail signal.

The ECC component 138 may perform error correction through a codedmodulation such as Low Density Parity Check (LDPC) code,Bose-Chaudhri-Hocquenghem (BCH) code, turbo code, Reed-Solomon code,convolution code, Recursive Systematic Code (RSC), Trellis-CodedModulation (TCM) and Block coded modulation (BCM). However, the ECCcomponent 138 is not limited to any specific structure. The ECCcomponent 138 may include all circuits, modules, systems or devices forerror correction.

The PMU 140 may provide and manage power of the controller 130.

The memory I/F 142 may serve as a memory/storage interface forinterfacing the controller 130 and the memory device 150 such that thecontroller 130 controls the memory device 150 in response to a requestfrom the host 102. When the memory device 150 is a flash memory orspecifically a NAND flash memory, the memory I/F 142 may generate acontrol signal for the memory device 150 and process data to be providedto the memory device 150 under the control of the processor 134. Thememory I/F 142 may work as an interface (e.g., a NAND flash interface)for processing a command and data between the controller 130 and thememory device 150. Specifically, the memory I/F 142 may support datatransfer between the controller 130 and the memory device 150.

The memory 144 may serve as a working memory of the memory system 110and the controller 130, and store data for driving the memory system 110and the controller 130. The controller 130 may control the memory device150 to perform read, write, program and erase operations in response toa request from the host 102. The controller 130 may provide data readfrom the memory device 150 to the host 102, may store data provided fromthe host 102 into the memory device 150. The memory 144 may store datarequired for the controller 130 and the memory device 150 to performthese operations.

The memory 144 may be embodied by a volatile memory. For example, thememory 144 may be embodied by static random access memory (SRAM) ordynamic random access memory (DRAM).

The memory 144 may be disposed within or out of the controller 130. FIG.1 exemplifies the memory 144 disposed within the controller 130. In anembodiment, the memory 144 may be embodied by an external volatilememory having a memory interface transferring data between the memory144 and the controller 130.

The processor 134 may control the overall operations of the memorysystem 110. The processor 134 may drive firmware to control the overalloperations of the memory system 110. The firmware may be referred to asflash translation layer (FTL). Also, the processor 134 may be realizedas a microprocessor or a Central Processing Unit (CPU).

For example, the controller 130 may perform an operation requested bythe host 102 in the memory device 150 through the processor 134, whichis realized as a microprocessor or a CPU. In other words, the controller130 may perform a command operation corresponding to a command receivedfrom the host 102, or other source. The controller 130 may perform aforeground operation as the command operation corresponding to thecommand received from the host 102. For example, the controller 130 mayperform a program operation corresponding to a write command, a readoperation corresponding to a read command, an erase operationcorresponding to an erase command, and a parameter set operationcorresponding to a set parameter command or a set feature command.

Also, the controller 130 may perform a background operation onto thememory device 150 through the processor 134, which is realized as amicroprocessor or a CPU. The background operation performed onto thememory device 150 may include an operation of copying and processingdata stored in some memory blocks among the memory blocks 152 to 156 ofthe memory device 150 into other memory blocks, e.g., a garbagecollection (GC) operation, an operation of swapping between the memoryblocks 152 to 156 or between the data of the memory blocks 152 to 156,e.g., a wear-leveling (WL) operation, an operation of storing the mapdata stored in the controller 130 in the memory blocks 152 to 156, e.g.,a map flush operation, or an operation of managing bad blocks of thememory device 150, e.g., a bad block management operation of detectingand processing bad blocks among the memory blocks 152 to 156.

Also, in the memory system in accordance with an embodiment of thepresent invention, for example, the controller 130 may perform aplurality of command operations corresponding to a plurality of commandsreceived from the host 102, e.g., a plurality of program operationscorresponding to a plurality of write commands, a plurality of readoperations corresponding to a plurality of read commands, and aplurality of erase operations corresponding to a plurality of erasecommands, in the memory device 150, and update metadata, particularly,map data, according to the performance of the command operations.

In particular, in the memory system in accordance with an embodiment ofthe present invention, when the controller 130 performs commandoperations corresponding to a plurality of commands received from thehost 102, e.g., program operations, read operations, and eraseoperations, in the memory blocks, the operation reliability of thememory device 150 may be deteriorated and also the utility efficiency ofthe memory device 150 may decrease, because characteristics aredeteriorated in the memory blocks due to the performance of the commandoperations. Therefore, a copy operation or a swap operation may beperformed in the memory device 150 according to the parameters for thememory device 150 according to the performance of the commandoperations.

Also, in the memory system in accordance with an embodiment of thepresent invention, when the controller 130 performs read operationscorresponding to a plurality of read commands received from the host 102in the memory blocks, particularly, when the controller 130 repeatedlyperforms read operations in some particular memory blocks, readdisturbance may be caused in the particular memory blocks due to therepeated read operations. Therefore, the controller 130 may perform aread reclaim operation to protect the particular memory blocks fromlosing data due to the read disturbance. In other words, in the memorysystem in accordance with an embodiment of the present invention, thecontroller 130 may copy and store the data stored in the particularmemory blocks into other memory blocks through the read reclaimoperation. In short, the controller 130 may perform a copy operation forthe particular memory blocks in the memory device 150.

In the memory system in accordance with an embodiment of the presentinvention, since the performance of the command operations correspondingto a plurality of commands received from the host 102 and theperformance of the swap operation and the copy operation performed inthe memory device 150 according to the parameters corresponding to theperformance of the command operations will be described in detail laterwith reference to FIGS. 5 to 8, further description on it is omittedhere.

The processor 134 of the controller 130 may include a management unit(not illustrated) for performing a bad management operation of thememory device 150. The management unit may perform a bad blockmanagement operation of checking a bad block, in which a program failoccurs due to a characteristic of the memory device, for example, a NANDflash memory during a program operation, among the plurality of memoryblocks 152 to 156 included in the memory device 150. The management unitmay write the program-failed data of the bad block to a new memoryblock. In a memory device 150 having a 3D stack structure, the bad blockmanagement operation may reduce the use efficiency of the memory device150 and the reliability of the memory system 110. Thus, the bad blockmanagement operation needs to be performed with more reliability. Amemory device of the memory system in accordance with an embodiment ofthe present invention is described in detail with reference to FIGS. 2to 4.

FIG. 2 is a schematic diagram illustrating the memory device 150, FIG. 3is a circuit diagram illustrating an exemplary configuration of a memorycell array of a memory block in the memory device 150, and FIG. 4 is aschematic diagram illustrating an exemplary 3D structure of the memorydevice 150.

Referring to FIG. 2, the memory device 150 may include a plurality ofmemory blocks 0 to N-1, e.g., a memory block 0 (BLK0) 210, a memoryblock 1 (BLK1) 220, a memory block 2 (BLK2) 230, and a memory block N-1(BLKN-1) 240. Each of the memory blocks 210, 220, 230 and 240 mayinclude a plurality of pages, for example 2^(M) pages, the number ofwhich may vary according to circuit design. For example in someapplications, each of the memory blocks may include M pages. Each of thepages may include a plurality of memory cells that are coupled to aplurality of word lines WL.

Also, the memory device 150 may include a plurality of memory blocks,which may include a single level cell (SLC) memory block storing 1-bitdata and/or a multi-level cell (MLC) memory block storing 2-bit data.The SLC memory blocks may include a plurality of pages that are realizedby memory cells storing one-bit data in one memory cell. The SLC memoryblocks may have a quick data operation performance and high durability.On the other hand, the MLC memory blocks may include a plurality ofpages that are realized by memory cells storing multi-bit data, e.g.,data of two or more bits, in one memory cell. The MLC memory blocks mayhave a greater data storing space than the SLC memory blocks. In otherwords, the MLC memory blocks may be highly integrated. Particularly, thememory device 150 may include not only the MLC memory blocks, each ofwhich includes a plurality of pages that are realized by memory cellscapable of storing two-bit data in one memory cell, but also triplelevel cell (TLC) memory blocks each of which includes a plurality ofpages that are realized by memory cells capable of storing three-bitdata in one memory cell, quadruple level cell (QLC) memory blocks eachof which includes a plurality of pages that are realized by memory cellscapable of storing four-bit data in one memory cell, and/or multiplelevel cell memory blocks each of which includes a plurality of pagesthat are realized by memory cells capable of storing five or more-bitdata in one memory cell, and so forth.

In accordance with an embodiment of the present invention, the memorydevice 150 is described as a non-volatile memory, such as a flashmemory, e.g., a NAND flash memory. However, the memory device 150 may berealized as any of a Phase Change Random Access Memory (PCRAM), aResistive Random Access Memory (RRAM or ReRAM), a Ferroelectric RandomAccess Memory (FRAM), a Spin Transfer Torque Magnetic Random AccessMemory (STT-RAM or STT-MRAM).

The memory blocks 210, 220, 230 and 240 may store the data transferredfrom the host 102 through a program operation, and transfer data storedtherein to the host 102 through a read operation.

Referring to FIG. 3, a memory block 330 which may correspond to any ofthe plurality of memory blocks 152 to 156 included in the memory device150 of the memory system 110 may include a plurality of cell strings 340coupled to a plurality of corresponding bit lines BL0 to BLm-1. The cellstring 340 of each column may include one or more drain selecttransistors DST and one or more source select transistors SST. Betweenthe drain and select transistors DST and SST, a plurality of memorycells MC0 to MCn-1 may be coupled in series. In an embodiment, each ofthe memory cell transistors MC0 to MCn-1 may be embodied by an MLCcapable of storing data information of a plurality of bits. Each of thecell strings 340 may be electrically coupled to a corresponding bit lineamong the plurality of bit lines BLO to BLm-1. For example, asillustrated in FIG. 3, the first cell string is coupled to the first bitline BLO, and the last cell string is coupled to the last bit lineBLm-1.

Although FIG. 3 illustrates NAND flash memory cells, the invention isnot limited in this way. It is noted that the memory cells may be NORflash memory cells, or hybrid flash memory cells including two or moretypes of memory cells combined therein. Also, it is noted that thememory device 150 may be a flash memory device including a conductivefloating gate as a charge storage layer or a charge trap flash (CTF)memory device including an insulation layer as a charge storage layer.

The memory device 150 may further include a voltage supply 310 whichprovides word line voltages including a program voltage, a read voltageand a pass voltage to supply to the word lines according to an operationmode. The voltage generation operation of the voltage supply 310 may becontrolled by a control circuit (not illustrated). Under the control ofthe control circuit, the voltage supply 310 may select one of the memoryblocks (or sectors) of the memory cell array, select one of the wordlines of the selected memory block, and provide the word line voltagesto the selected word line and the unselected word lines as may beneeded.

The memory device 150 may include a read/write circuit 320 which iscontrolled by the control circuit. During a verification/normal readoperation, the read/write circuit 320 may operate as a sense amplifierfor reading data from the memory cell array. During a program operation,the read/write circuit 320 may operate as a write driver for driving bitlines according to data to be stored in the memory cell array. During aprogram operation, the read/write circuit 320 may receive from a buffer(not illustrated) data to be stored into the memory cell array, anddrive bit lines according to the received data. The read/write circuit320 may include a plurality of page buffers 322 to 326 respectivelycorresponding to columns (or bit lines) or column pairs (or bit linepairs), and each of the page buffers 322 to 326 may include a pluralityof latches (not illustrated).

The memory device 150 may be embodied by a 2D or 3D memory device.Particularly, as illustrated in FIG. 4, the memory device 150 may beembodied by a nonvolatile memory device having a 3D stack structure.When the memory device 150 has a 3D structure, the memory device 150 mayinclude a plurality of memory blocks BLK0 to BLKN-1. FIG. 4 is a blockdiagram illustrating the memory blocks 152 to 156 of the memory device150 shown in FIG. 1. Each of the memory blocks 152 to 156 may berealized in a 3D structure (or vertical structure). For example, thememory blocks 152 to 156 may be a three-dimensional structure withdimensions extending in first to third directions, e.g., an x-axisdirection, a y-axis direction, and a z-axis direction.

Each memory block 330 included in the memory device 150 may include aplurality of NAND strings NS that are extended in the second direction,and a plurality of NAND strings NS that are extended in the firstdirection and the third direction. Each of the NAND strings NS may becoupled to a bit line BL, at least one string selection line SSL, atleast one ground selection line GSL, a plurality of word lines WL, atleast one dummy word line DWL, and a common source line CSL, and each ofthe NAND strings NS may include a plurality of transistor structures TS.

In short, each memory block 330 among the memory blocks 152 to 156 ofthe memory device 150 may be coupled to a plurality of bit lines BL, aplurality of string selection lines SSL, a plurality of ground selectionlines GSL, a plurality of word lines WL, a plurality of dummy word linesDWL, and a plurality of common source lines CSL, and each memory block330 may include a plurality of NAND strings NS. Also, in each memoryblock 330, one bit line BL may be coupled to a plurality of NAND stringsNS to realize a plurality of transistors in one NAND string NS. Also, astring selection transistor SST of each NAND string NS may be coupled toa corresponding bit line BL, and a ground selection transistor GST ofeach NAND string NS may be coupled to a common source line CSL. Memorycells MC may be provided between the string selection transistor SST andthe ground selection transistor GST of each NAND string NS. In otherwords, a plurality of memory cells may be realized in each memory block330 of the memory blocks 152 to 156 of the memory device 150. A dataprocessing operation toward a memory device, particularly, a dataprocessing operation performed when a plurality of command operationscorresponding to a plurality of commands are performed, in a memorysystem in accordance with an embodiment of the present invention isdescribed in detail with reference to FIGS. 5 to 8.

FIGS. 5 to 7 illustrate an example of a data processing operation when aplurality of command operations corresponding to a plurality of commandsare performed in a memory system in accordance with an embodiment of thepresent invention. In accordance with an embodiment of the presentinvention, for the sake of convenience, a case where a plurality ofcommands are received from the host 102 and command operationscorresponding to the received commands are performed in the memorysystem 110 of FIG. 1 are shown as an example and is described in detail.For example, a plurality of write commands may be received from the host102 and program operations corresponding to the write commands may beperformed, or a plurality of read commands may be received from the host102 and read operations corresponding to the read commands may beperformed, or a plurality of erase commands may be received from thehost 102 and erase operations corresponding to the erase commands may beperformed, or a plurality of write commands and a plurality of readcommands may be received together from the host 102 and programoperations and read operations corresponding to the write commands andthe read commands may be performed.

Also, cases where write data corresponding to a plurality of writecommands received from the host 102 are stored in a buffer/cacheincluded in the memory 144 of the controller 130, and then the datastored in the buffer/cache are programmed and stored in a plurality ofmemory blocks (in short, program operations are performed), and alsowhere map data are updated corresponding to the program operations intothe memory device 150 and then the updated map data are stored in thememory blocks are provided as examples. In short, performing programoperations corresponding to a plurality of write commands is shown as anexample and described.

Also, a case where when a plurality of read commands are received fromthe host 102 for the data stored in the memory device 150, the datacorresponding to the read commands are read from the memory device 150by detecting the map data for the data corresponding to the readcommands and the read data are stored in the buffer/cache included inthe memory 144 of the controller 130 and the data stored in thebuffer/cache are transferred to the host 102 is shown as an example anddescribed in an embodiment of the present invention. In short, a casewhere read operations corresponding to the read commands are performedis shown as an example and described in an embodiment of the presentinvention.

Also, a case where when a plurality of erase commands are received fromthe host 102, the memory blocks corresponding to the erase commands aredetected and the data stored in the detected memory blocks are erasedand the map data are updated corresponding to the erased data and theupdated map data are stored in the memory blocks is shown as an exampleand described in an embodiment of the present invention. In short, acase where erase operations corresponding to the erase commands areperformed is shown as an example and described in an embodiment of thepresent invention.

It is assumed in an embodiment of the present invention for the sake ofconvenience that the command operations performed in the memory system110 are performed by the controller 130. However, this is merely anexample and, as described above, the processor 134 included in thecontroller 130, e.g., the FTL, may perform the command operations.

Also, in an embodiment of the present invention, the controller 130 mayprogram and store the user data corresponding to the write commands andthe metadata in some memory blocks among the memory blocks, read theuser data corresponding to the read commands and the metadata from thememory blocks storing the user data and the metadata among the memoryblocks and transfer the read user data and the metadata to the host 102,or erase the user data corresponding to the erase commands and metadatafrom the memory blocks storing the user data and the metadata among thememory blocks.

The metadata may include a first map data including Logical to Physical(L2P) information (which is called logical information, hereafter) forthe data stored in memory blocks through a program operation, and asecond map data including Physical to Logical (P2L) information (whichis called physical information, hereafter). Also, the metadata mayinclude information on the command data corresponding to a command,information on a command operation corresponding to the command,information on the memory blocks where the command operation isperformed, and information on the map data corresponding to the commandoperation. In other words, the metadata may include all the otherinformation and data except the user data corresponding to a command.

According to an embodiment of the present invention, the controller 130may perform command operations corresponding to a plurality of commands.For example, when the controller 130 receives write commands from thehost 102, the controller 130 may perform program operationscorresponding to the write commands. The controller 130 may program andstore user data corresponding to the write commands in the memoryblocks, such as empty memory blocks where an erase operation isperformed, open memory blocks, or free memory blocks. Also, thecontroller 130 may program and store mapping information between thelogical addresses and the physical addresses for the user data stored inthe memory blocks (which are first map data including an L2P map tableor an L2P map list containing logical information) and mappinginformation between the physical addresses and the logical addresses forthe memory blocks storing the user data (which are second map dataincluding a P2L map table or a P2L map list containing physicalinformation) in the empty memory blocks, open memory blocks, or freememory blocks among the memory blocks.

When the controller 130 receives write commands from the host 102, thecontroller 130 may program and store user data corresponding to thewrite commands in the memory blocks and store metadata that includes thefirst map data and the second map data for the user data stored in thememory blocks in memory blocks. Particularly, since data segments of theuser data are stored in the memory blocks, the controller 130 maygenerate and update meta segments of the meta data, which are mapsegments of map data including L2P segments of the first map data andP2L segments of the second map data, and store them in the memoryblocks. The map segments stored in the memory blocks may be loaded ontothe memory 144 of the controller 130 to be updated.

Also, when the controller 130 receives a plurality of read commands fromthe host 102, the controller 130 may read out the read datacorresponding to the read commands from the memory device 150, store theread data in the buffer/cache included in the memory 144 of thecontroller 130, transfer the data stored in the buffer/cache to the host102. In this way, read operations may be performed.

Also, when the controller 130 receives a plurality of erase commandsfrom the host 102, the controller 130 may detect memory blocks thatcorrespond to the erase commands and perform erase operations onto thedetected memory blocks. A data processing operation performed in thememory system in accordance with embodiments of the present invention isdescribed in detail with reference to FIGS. 5 to 7.

Referring to FIG. 5, the controller 130 may perform command operationscorresponding to a plurality of commands received from the host 102. Forexample, the controller 130 may perform program operations correspondingto a plurality of write commands. The controller 130 may program andstore user data corresponding to the write commands in memory blocks,and generate and update metadata for the user data when the programoperations are performed on the memory blocks, and then store thegenerated and updated metadata in the memory blocks.

The controller 130 may generate and update first map data and second mapdata that include information representing that the user data are storedin the pages included in the memory blocks. In other words, thecontroller 130 may generate and update logical segments of the first mapdata, which include L2P segments and physical segments of the second mapdata, which include P2L segments, and store the generated and updatedlogical segments in the pages included in the memory blocks.

For example, the controller 130 may cache and buffer the user datacorresponding to the write commands in the first buffer 510 included inthe memory 144 of the controller 130. In other words, the controller 130may store the data segments 512 of the user data in the first buffer510, which is a data buffer/cache, and store the data segments 512stored in the first buffer 510 in the pages included in the memoryblocks. Since the data segments 512 of the user data corresponding tothe write commands are programmed and stored in the pages included inthe memory blocks, the controller 130 may generate and update the firstmap data and the second map data and store them in the second buffer 520included in the memory 144 of the controller 130. In short, thecontroller 130 may store the L2P segments 522 of the first map data andthe P2L segments 524 of the second map data for the user data in thesecond buffer 520, which is a map buffer/cache. As described above, theL2P segments 522 of the first map data and the P2L segments 524 of thesecond map data or a map list for the L2P segments 522 of the first mapdata and a map list for the P2L segments 524 of the second map data maybe stored in the second buffer 520 in the memory 144 of the controller130. Also, the controller 130 may store the L2P segments 522 of thefirst map data and the P2L segments 524 of the second map data that arestored in the second buffer 520 in the pages included in the memoryblocks.

Also, the controller 130 may perform command operations corresponding toa plurality of commands received from the host 102. For example, thecontroller 130 may perform read operations corresponding to a pluralityof read commands. The controller 130 may load and check out the mapsegments of the map data for the user data corresponding to the readcommands, e.g., the L2P segments 522 of the first map data and the P2Lsegments 524 of the second map data, onto the second buffer 520, andthen read the user data stored in the pages of the corresponding memoryblocks among the memory blocks, store the data segments 512 of the readuser data in the first buffer 510, and transfer them to the host 102.

In addition, the controller 130 may perform command operationscorresponding to a plurality of commands received from the host 102. Inother words, the controller 130 may perform erase operationscorresponding to a plurality of erase commands. The controller 130 maydetect memory blocks corresponding to the erase commands among thememory blocks, and perform the erase operations on the detected memoryblocks.

When a background operation, for example, an operation of copying dataor swapping data from the memory blocks, such as a garbage collectionoperation or a wear-leveling operation, is performed, the controller 130may store the data segments 512 of the corresponding user data in thefirst buffer 510, load the map segments 522 and 524 of the map datacorresponding to the user data onto the second buffer 520, and performthe garbage collection operation or the wear-leveling operation.

As described above, when performing the command operations on the memoryblocks, the controller 130 may repeatedly perform the command operationson specific memory blocks. Particularly, when the controller 130repeatedly performs the read operations on the specific memory blocks,read disturbances may occur in the specific memory blocks. Thecontroller 130 may detect parameters for each memory block correspondingto performance of the command operations among the memory blocks, andthen perform a copy operation on the memory blocks based on theparameters for the memory blocks. Particularly, the controller 130 maydetect read counts for each memory block, corresponding to performanceof the read operation, and copy and store data stored in the specificmemory blocks in another specific memory blocks based on the readcounts. In other words, the controller 130 may perform a read reclaimoperation on the specific memory blocks based on the read counts foreach memory block.

Referring to FIG. 6, the memory device 150 may include a plurality ofmemory dies, e.g., a memory die 0, a memory die 1, a memory die 2, and amemory die 3. Each of the memory dies may include a plurality of planes,e.g., a plane 0, a plane 1, a plane 2, and a plane 3. Each of the planesof the memory dies may include a plurality of memory blocks. Forexample, as described earlier with reference to FIG. 2, each of theplanes may include N blocks: BLK0, BLK1, . . . , BLKN-1, each includinga plurality of pages, e.g., 2^(M) pages.

The memory device 150 may also include a plurality of buffers thatrespectively correspond to the memory dies. For example, the memorydevice 150 may include a buffer 0 corresponding to the memory die 0, abuffer 1 corresponding to the memory die 1, a buffer 2 corresponding tothe memory die 2, and a buffer 3 corresponding to the memory die 3.

When the command operations corresponding to the plurality of commandsare performed, data corresponding to the command operations may bestored in the buffers included in the memory device 150. For example,when the program operations are performed, data corresponding to theprogram operations may be stored in the buffers, and then stored in thepages included in the memory blocks of the memory dies. When readoperations are performed, data corresponding to the read operations maybe read from the pages included in the memory blocks of the memory dies,stored in the buffers, and transferred to the host 102 through thecontroller 130.

In an embodiment of the present invention, for the sake of convenience,a case where the buffers in the memory device 150 exist outside of thecorresponding memory dies is shown as an example and described. However,the buffers in the memory device 150 may exist inside of thecorresponding memory dies. Also, the buffers may correspond to theplanes or the memory blocks in the memory dies. In an embodiment of thepresent invention, for the sake of convenience, a case where the buffersin the memory device 150 are a plurality of page buffers is described asan example, as described earlier with reference to FIG. 3. However, thebuffers in the memory device 150 may be a plurality of caches or aplurality of registers.

Also, the memory blocks may be grouped into a plurality of super memoryblocks, and then the command operations may be performed on the supermemory blocks. Each of the super memory blocks may include a pluralityof memory blocks, for example, memory blocks included in a first memoryblock group and a second memory block group. When the first memory blockgroup is included in a first plane of a first memory die, the secondmemory block group may be included in the first plane of the firstmemory die, a second plane of the first memory die, or planes of asecond memory die. As described earlier, when the command operationscorresponding to the commands are performed on the memory blocks, theparameters for each memory block corresponding to the performance of thecommand operations may be detected, and then the copy operation may beperformed on the memory blocks based on the parameters. Further detailis provided with reference to FIG. 7.

Referring to FIG. 7, when the controller 130 receives a plurality ofread commands from the host 102, the controller 130 may perform readoperations on a plurality of memory blocks.

The controller 130 may detect parameters for the memory blocks based onthe read operations performed on the memory blocks, and then perform acopy operation on the memory blocks based on the parameters.

Particularly, the controller 130 may detect read counts for the memoryblocks of the memory device based on the read operation performed on thememory blocks, and then perform a read reclaim operation on the memoryblocks based on the read counts.

More specifically, the controller 130 may perform the read operations onthe memory blocks, for example, a memory block 10, a memory block 11, amemory block 12, a memory block 13, a memory block 14, a memory block15, a memory block 16, a memory block 17, a memory block 18, a memoryblock 19, a memory block 20 and a memory block 21.

The controller 130 may detect the read counts for each memory blockbased on performance of the read operations, and then record the readcounts for the memory blocks in a parameter table 700 for the memoryblocks. The controller 130 may store the parameter table 700 in thememory 144, and may control the memory device 150 to store the parametertable 700 therein by including the parameter table 700 in metadata. Theparameter table 700 includes an index 702 of the memory blocks, and readcounts 704, in which a record of the read count of each memory block isrecorded.

For example, as described above, when the controller 130 receives theread commands from the host 102, the controller 130 may read datacorresponding to the read commands from the pages included in the memoryblocks, and then transfer the read data to the host 102 in response tothe read commands, thereby performing the read operations on the memoryblocks.

The controller 130 may record the parameters corresponding to theperformance of the read operation, i.e., the read counts 704, in theparameter table 700.

In other words, when the controller 130 performs the read operations onthe memory blocks, the controller 130 may detect the read counts 704 foreach memory block of the memory device 150, and then record each of theread counts 704 in the parameter table 700 for each of the memoryblocks, which are referenced in index 702.

When the controller 130 repeatedly performs the read operations on thememory blocks, read disturbances may occur in the memory blocks. Forthis reason, the controller 130 may perform the copy operation on thememory blocks based on the parameters for the memory blocks, i.e., theread counts 704 recorded in the parameter table 700. In other words, thecontroller 130 may perform the copy operation as the read reclaimoperation on the memory blocks based on the read counts 704 recorded inthe parameter table 700.

When a power state of the memory system 110 changes, that is, the memorysystem 110 changes from a power-on state to a power-off state due tosudden power off occurring in the memory system 110, and then changes tothe power-on state again, the read counts 704 recorded in the parametertable 700 may be initialized.

Accordingly, when the controller 130 performs the read operations on thememory blocks, the controller 130 may apply a first voltage to a dummyregion that is set in each of the memory blocks, and detect the readdisturbances from the memory blocks based on the first voltage appliedto the dummy region. The controller 130 may perform the copy operationon the memory blocks according to the read disturbances of the memoryblocks. Particularly, the controller 130 may perform the copy operationas the read reclaim operation on the memory blocks according to the readdisturbances of the memory blocks.

The controller 130 may adjust the read counts 704 recorded in theparameter table 700 according to the read disturbances for each memoryblock of the memory device 150, and perform the copy operation as theread reclaim operation on the memory blocks based on the adjusted readcounts.

For example, when the controller 130 performs the read operations on thememory blocks after the initialization of the parameter table 700 due tothe change of the power state of the memory system 110, the controller130 may apply the first voltage to the dummy region in each of thememory blocks. For example, as described above, when each of the memoryblocks arranged in a cell array includes a plurality of word lines, oreach of the memory blocks is includes a plurality of pages each of whichincludes memory cells formed by the word lines, the dummy region may beset in the word lines or the pages. In other words, the dummy region maybe set as a dummy word line in the word lines included in each of thememory blocks or a dummy page in the pages included in each of thememory blocks.

The dummy region may be set as a 1-bit region or a predetermined bitregion in a first word line among the word lines included in each of thememory blocks or a 1-bit region or a predetermined bit region in a firstpage among the pages included in each of the memory blocks.

When the dummy region includes the 1-bit region or the predetermined bitregion in each of the memory blocks, the dummy word line may be addedprevious to the first word line in each of the memory blocks, and thedummy page may be added previous to the first page in each of the memoryblocks.

When the dummy word line is added previous to the first word line, orthe dummy page is added previous to the first page, the commandoperations may be first performed on the first word line and the firstpage in each of the memory blocks. For example, when data are to bestored in each of the memory blocks, the data may be first stored in thefirst word line and the first page.

In addition, when the word lines included in each of the memory blocksare grouped into a plurality of word line groups, or the pages includedin each of the memory blocks are grouped into a plurality of pagegroups, the dummy word line may be set for each word line group, or thedummy page may be set for each page group.

When the command operations are performed on each of the memory blocks,the first voltage applied to the dummy region may become a pass voltagehaving a maximum level at or higher than a maximum level of a commandoperation voltage among command operation voltages of each of the memoryblocks.

For example, the first voltage may become a pass voltage having amaximum level at or higher than a maximum level of a command operationvoltage among program voltages, with which the program operations areperformed on each of the memory blocks, a pass voltage having a maximumlevel at or higher than a maximum level of a command operation voltageamong erase voltages, with which the erase operations are performed oneach of the memory blocks, or a pass voltage having a maximum level ator higher than a maximum level of a command operation voltage among readvoltages, with which the read operations are performed on each of thememory blocks.

In an embodiment of the present invention the first voltage becomes apass voltage (Vpass) 706 having a maximum level at or higher than amaximum level of a read voltage among the read voltages, with which theread operations are performed on each of the memory blocks. The passvoltages (Vpass) 706 may be included in a is field of the parametertable 700 as shown in FIG. 7.

When the read operations are performed on each of the memory blocks, thecontroller 130 may apply the pass voltage 706 corresponding to each ofthe memory blocks to the dummy word line or the dummy page in each ofthe memory blocks. The controller 130 may apply the pass voltage 706having the maximum level among the voltage levels, which are to beapplied to each of the memory blocks, to the dummy word line or thedummy page in each of the memory blocks when the read operations areperformed on each of the memory blocks.

Also, when the dummy word line is set for each word line group in eachof the memory blocks, or the dummy page is set for each page group ineach of the memory blocks, the controller 130 may apply the pass voltage706 having the maximum level for each word line group or each page groupto the dummy word line for each word line group or the dummy page foreach page group.

Besides, the controller 130 may detect the read disturbance 708 fromeach of the memory blocks based on the pass voltage 706 applied to thedummy word line or the dummy page of each of the memory blocks.

The controller 130 may record the pass voltage 706 applied to the dummyword line or the dummy page of each of the memory blocks in theparameter table 700. The controller 130 may record the read disturbance708 detected from each of the memory blocks in the parameter table 700based on the pass voltage 706 applied to the dummy word line or thedummy page of each of the memory blocks.

When the pass voltage 706 is applied to the dummy word line for eachword line group or the dummy page for each page group, the controller130 may detect the read disturbances for each word line group or eachpage group from each of the memory blocks, and detect a maximum readdisturbance or an average read disturbance among the read disturbancesdetected for each word line group or each page group as the readdisturbance 708 of each of the memory blocks.

The controller 130 may perform the read reclaim operation on the memoryblocks based on the read disturbance 708 for each memory block. Thecontroller 130 may perform the read reclaim operation on each of thememory blocks whose read disturbance 708 is equal to or greater than athreshold value.

Also, the controller 130 may adjust the read counts 704 for each memoryblock recorded in the parameter table 700 based on the read disturbance708 for each memory block, and perform the read reclaim operation on thememory blocks based on the adjusted read counts 710.

The controller 130 may record the adjusted read counts 710 in theparameter table 700.

When the read operations are performed on the memory blocks, thecontroller 130 may detect the read counts 704 of the memory blocks asparameters for the memory blocks, and then perform the copy operation oneach of the memory blocks based on the read counts 704.

Also, the controller 130 may apply the pass voltage 706 having themaximum level to the dummy word line or the dummy page of each of thememory blocks when the read operations are performed on each of thememory blocks.

Subsequently, the controller 130 may detect a voltage offset or avoltage distribution offset as a parameter of the read disturbance 708or a read error corresponding to the applied pass voltage for each ofthe memory blocks, and perform the copy operation on each of the memoryblocks based on the read disturbance 708 or the read error detected fromeach of the memory blocks.

The controller 130 may adjust the read count of each of the memoryblocks based on the read disturbance 708 or the read error detected fromeach of the memory blocks, and then perform the copy operation on thememory blocks based on the adjusted read counts of the memory blocks.

As described above, the controller 130 may perform the copy operation oneach of the memory blocks based on the read disturbance 708 or the readerror (Le., the voltage offset or the voltage distribution offset) whenthe power state of the memory system 110 is changed such that the readcount for each of the memory blocks is initialized.

When the read count for each of the memory blocks is a parameter that isnormally counted, the controller 130 may adjust the read count based onthe read disturbance 708 or the read error, and then perform the copyoperation on each of the memory blocks based on the adjusted read count.

Although it is described in an embodiment of the present invention thatthe read operations are performed on the memory blocks, the inventiveconcept may be also applied to cases where the program operations, theerase operations and the background operations are performed on thememory blocks.

In other words, when the program operations corresponding to the writecommands are performed on the memory blocks, the controller 130 maydetect a program count or a write count as a parameter for each of thememory blocks, and then perform the copy operation on each of the memoryblocks based on the program count.

Also, the controller 130 may apply the pass voltage having the maximumlevel to the dummy word line or the dummy page of each of the memoryblocks as the dummy region when the program operations are performed onthe memory blocks, and then detect the voltage offset or the voltagedistribution offset as the parameter for each of the memory blockscorresponding to the applied pass voltage, and perform the copyoperation on each of the memory blocks based on the voltage offset orthe voltage distribution offset detected from each of the memory blocks.

In case of the program operation, the voltage offset or the voltagedistribution offset detected from each of the memory blocks may bedetected as a program error through the pass voltage applied to thedummy word line or the dummy page of each of the memory blocks.

The controller 130 may adjust the program count of each of the memoryblocks based on the voltage offset or the voltage distribution offsetdetected from each of the memory blocks, and then may perform the copyoperation on the memory blocks based on the adjusted program counts ofthe memory blocks.

As described above, the controller 130 may perform the copy operation oneach of the memory blocks based on the voltage offset or the voltagedistribution offset when the power state of the memory system 110 ischanged such that the program count for each of the memory blocks isinitialized.

When the program count for each of the memory blocks is a parameter thatis normally counted, the controller 130 may adjust the program countbased on the voltage offset or the voltage distribution offset, and thenmay perform the copy operation on each of the memory blocks based on theadjusted program count.

In addition, when the erase operations corresponding to the erasecommands are performed on the memory blocks, the controller 130 maydetect an erase count as a parameter for each of the memory blocks, andthen perform the copy operation on each of the memory blocks based onthe erase count.

Also, the controller 130 may apply the pass voltage having the maximumlevel to the dummy word line or the dummy page of each of the memoryblocks as the dummy region when the erase operations are performed onthe memory blocks, and then detect the voltage offset or the voltagedistribution offset as the parameter for each of the memory blockscorresponding to the applied pass voltage, and perform the copyoperation on each of the memory blocks based on the read disturbance 708or the read error detected from each of the memory blocks.

In case of the erase operation, the voltage offset or the voltagedistribution offset detected from each of the memory blocks may bedetected as an erase error through the pass voltage applied to the dummyword line or the dummy page of each of the memory blocks.

The controller 130 may adjust the erase count of each of the memoryblocks based on the voltage offset or the voltage distribution offsetdetected from each of the memory blocks, and then may perform the copyoperation on the memory blocks based on the adjusted erase counts of thememory blocks.

As described above, the controller 130 may perform the copy operation oneach of the memory blocks based on the voltage offset or the voltagedistribution offset when the power state of the memory system 110 ischanged such that the erase count for each of the memory blocks isinitialized.

When the erase count for each of the memory blocks is a parameter thatis normally counted, the controller 130 may adjust the erase count basedon the voltage offset or the voltage distribution offset, and then mayperform the copy operation on each of the memory blocks based on theadjusted erase count.

As described above, when the copy operation is performed on each of thememory blocks, the controller 130 may select source memory blocks basedon the command operation count (e.g., the read count 704) as theparameter corresponding to the performance of the command operations ineach of the memory blocks and the voltage offset or the voltagedistribution offset (e.g., the read disturbance 708 or the read error)as the parameter corresponding to the pass voltage applied to the dummyregion when the command operations are performed, and then copy andstore data stored in the source memory blocks in the target memoryblocks.

For example, the controller 130 may select the source memory blocks fromthe memory block 10, the memory block 11, the memory block 12, thememory block 13, the memory block 14, the memory block 15, the memoryblock 16, the memory block 17, the memory block 18, the memory block 19,the memory block 20 and the memory block 21. Then the controller 130 maycopy and store the data stored in the source memory blocks in a memoryblock i−1, a memory block i and a memory block i+1 as the target memoryblocks. is The memory block i−1, the memory block i and the memory blocki+1 may be the blank memory blocks, the open memory blocks or the freememory blocks in the memory blocks. An operation of processing data inthe memory system is described in detail below with reference to FIG. 8.

FIG. 8 is a flowchart describing an operation of processing data in thememory system in accordance with an embodiment of the present invention.

Referring to FIG. 8, in step 810, the memory system 110 may receive aplurality of commands, for example, a plurality of write commands, aplurality of read commands and/or a plurality of erase commands, fromthe host 102.

In step S820, the memory system 110 may perform command operationscorresponding to the commands on memory blocks, and apply pass voltages706 having a maximum level to the dummy region of each of the memoryblocks when the command operations are performed.

In step S830, the memory system 110 may detect command operation counts(e.g., the read count 704) as parameters for the memory blockscorresponding to the performance of the command operations, and detectvoltage offsets or voltage distribution offsets (e.g., the readdisturbances 708) as the parameters for the memory blocks correspondingto the applied pass voltages.

In step S840, the memory system 110 may perform a copy operation on thememory blocks based on the command operations counts and the voltageoffsets as the parameters for the memory blocks.

Since performing the command operations corresponding to the commands,applying the pass voltages when the command operations are performed,detecting the command operation counts corresponding to the performanceof the command operations, detecting the voltage offsets or the voltagedistribution offsets corresponding to the applied pass voltages, andperforming the copy operation based on the command operation counts andthe voltage offsets are described above in detail with reference toFIGS. 5 to 7, overlapping descriptions will be omitted. A dataprocessing system and electronic devices to which the memory system 110including the memory device 150 and the controller 130, which aredescribed above with reference to FIGS. 1 to 8, will be described indetail with reference to FIGS. 9 to 17 in accordance with an embodimentof the invention.

FIG. 9 is a diagram schematically illustrating the data processingsystem including the memory system in accordance with an embodiment.FIG. 9 schematically illustrates a memory card system to which thememory system in accordance with an embodiment is applied.

Referring to FIG. 9, the memory card system 6100 may include a memorycontroller 6120, a memory device 6130 and a connector 6110.

More specifically, the memory controller 6120 may be connected to thememory device 6130 embodied by a nonvolatile memory, and configured toaccess the memory device 6130. For example, the memory controller 6120may be configured to control read, write, erase and backgroundoperations of the memory device 6130. The memory controller 6120 may beconfigured to provide an interface between the memory device 6130 and ahost, and drive firmware for controlling the memory device 6130. Thatis, the memory controller 6120 may correspond to the controller 130 ofthe memory system 110 described with reference to FIG. 1, and the memorydevice 6130 may correspond to the memory device 150 of the memory system110 described with reference to FIG. 1.

Thus, the memory controller 6120 may include a RAM, a processor, a hostinterface, a memory interface and an error correction component.

The memory controller 6120 may communicate with an external device, forexample the host 102 of FIG. 1, through the connector 6110. For example,as described with reference to FIG. 1, the memory controller 6120 may beconfigured to communicate with an external device through one or more ofvarious communication protocols such as universal serial bus (USB),multimedia card (MMC), embedded MMC (eMMC), peripheral componentinterconnection (PCI), PCI express (PCIe), Advanced TechnologyAttachment (ATA), Serial-ATA, Parallel-ATA, small computer systeminterface (SCSI), enhanced small disk interface (EDSI), Integrated DriveElectronics (IDE), Firewire, universal flash storage (UFS), WIFI andBluetooth. Thus, the memory system and the data processing system inaccordance with an embodiment may be applied to wired/wirelesselectronic devices or particularly mobile electronic devices.

The memory device 6130 may be implemented by a nonvolatile memory. Forexample, the memory device 6130 may be implemented by any of variousnonvolatile memory devices such as an erasable and programmable ROM(EPROM), an electrically erasable and programmable ROM (EEPROM), a NANDflash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistiveRAM (ReRAM), a ferroelectric RAM (FRAM) and a spin torque transfermagnetic RAM (STT-RAM).

The memory controller 6120 and the memory device 6130 may be integratedinto a single semiconductor device. For example, the memory controller6120 and the memory device 6130 may be integrated to form a solid-statedriver (SSD). Also, the memory controller 6120 and the memory device6130 may form a memory card such as a PC card (PCMCIA: Personal ComputerMemory Card International Association), a compact flash (CF) card, asmart media card (e.g., SM and SMC), a memory stick, a multimedia card(e.g., MMC, RS-MMC, MMCmicro and eMMC), an SD card (e.g., SD, miniSD,microSD and SDRC) and a universal flash storage (UFS).

FIG. 10 is a diagram schematically illustrating another example of thedata processing system including the memory system in accordance with anembodiment.

Referring to FIG. 10, the data processing system 6200 may include amemory device 6230 having one or more nonvolatile memories and a memorycontroller 6220 for controlling the memory device 6230. The dataprocessing system 6200 illustrated in FIG. 10 may serve as a storagemedium such as a memory card (CF, SD, micro-SD or the like) or USBdevice, as described with reference to FIG. 1. The memory device 6230may correspond to the memory device 150 in the memory system 110illustrated in FIG. 1, and the memory controller 6220 may correspond tothe controller 130 in the memory system 110 illustrated in FIG. 1.

The memory controller 6220 may control a read, write or erase operationon the memory device 6230 in response to a request of the host 6210, andthe memory controller 6220 may include one or more CPUs 6221, a buffermemory such as RAM 6222, an ECC circuit 6223, a host interface 6224 anda memory interface such as an NUM interface 6225.

The CPU 6221 may control overall operations on the memory device 6230,for example, read, write, file system management and bad page managementoperations. The RAM 6222 may be operated according to control of the CPU6221, and used as a work memory, buffer memory or cache memory. When theRAM 6222 is used as a is work memory, data processed by the CPU 6221 maybe temporarily stored in the RAM 6222. When the RAM 6222 is used as abuffer memory, the RAM 6222 may be used for buffering data transmittedto the memory device 6230 from the host 6210 or transmitted to the host6210 from the memory device 6230. When the RAM 6222 is used as a cachememory, the RAM 6222 may assist the low-speed memory device 6230 tooperate at high speed.

The ECC circuit 6223 may correspond to the ECC component 138 of thecontroller 130 illustrated in FIG. 1. As described with reference toFIG. 1, the ECC circuit 6223 may generate an ECC (Error Correction Code)for correcting a fail bit or error bit of data provided from the memorydevice 6230. The ECC circuit 6223 may perform error correction encodingon data provided to the memory device 6230, thereby forming data with aparity bit. The parity bit may be stored in the memory device 6230. TheECC circuit 6223 may perform error correction decoding on data outputtedfrom the memory device 6230. The ECC circuit 6223 may correct an errorusing the parity bit. For example, as described with reference to FIG.1, the ECC circuit 6223 may correct an error using the LDPC code, BCHcode, turbo code, Reed-Solomon code, convolution code, RSC or codedmodulation such as TCM or BCM.

The memory controller 6220 may transmit/receive data to/from the host6210 through the host interface 6224, and transmit/receive data to/fromthe memory device 6230 through the NVM interface 6225. The hostinterface 6224 may be connected to the host 6210 through a PATA bus,SATA bus, SCSI, USB, PCIe or NAND interface. The memory controller 6220may have a wireless communication function with a mobile communicationprotocol such as WiFi or Long Term Evolution (LTE). The memorycontroller 6220 may be connected to an external device, for example, thehost 6210 or another external device, and then transmit/receive datato/from the external device. In particular, as the memory controller6220 is configured to communicate with the external device through oneor more of various communication protocols, the memory system and thedata processing system in accordance with an embodiment may be appliedto wired/wireless electronic devices or particularly a mobile electronicdevice.

FIG. 11 is a diagram schematically illustrating another example of thedata processing system including the memory system in accordance with anembodiment. FIG. 11 schematically illustrates an SSD to which the memorysystem may be applied.

Referring to FIG. 11, the SSD 6300 may include a controller 6320 and amemory device 6340 including a plurality of nonvolatile memories. Thecontroller 6320 may correspond to the controller 130 in the memorysystem 110 of FIG. 1, and the memory device 6340 may correspond to thememory device 150 in the memory system of FIG. 1.

More specifically, the controller 6320 may be connected to the memorydevice 6340 through a plurality of channels CH1 to CHi. The controller6320 may include one or more processors 6321, a buffer memory 6325, anECC circuit 6322, a host interface 6324 and a memory interface, forexample, a nonvolatile memory interface 6326.

The buffer memory 6325 may temporarily store data provided from the host6310 or data provided from a plurality of flash memories NVM included inthe memory device 6340, or temporarily store meta data of the pluralityof flash memories NVM, for example, map data including a mapping table.The buffer memory 6325 may be embodied by volatile memories such asDRAM, SDRAM, DDR SDRAM, LPDDR SDRAM and GRAM or nonvolatile memoriessuch as FRAM, ReRAM, STT-MRAM and PRAM. For convenience of description,FIG. 11 illustrates that the buffer memory 6325 exists in the controller6320. However, the buffer memory 6325 may exist outside the controller6320.

The ECC circuit 6322 may calculate an ECC value of data to be programmedto the memory device 6340 during a program operation, perform an errorcorrection operation on data read from the memory device 6340 based onthe ECC value during a read operation, and perform an error correctionoperation on data recovered from the memory device 6340 during a faileddata recovery operation.

The host interface 6324 may provide an interface function with anexternal device, for example, the host 6310, and the nonvolatile memoryinterface 6326 may provide an interface function with the memory device6340 connected through the plurality of channels.

Furthermore, a plurality of SSDs 6300 to which the memory system 110 ofFIG. 1 is applied may be provided to embody a data processing system,for example, RAID (Redundant Array of Independent Disks) system. At thistime, the RAID system may include the plurality of SSDs 6300 and a RAIDcontroller for controlling the plurality of SSDs 6300. When the RAIDcontroller performs a program operation in response to a write commandprovided from the host 6310, the RAID controller may select one or morememory systems or SSDs 6300 according to a plurality of RAID levels,that is, RAID level information of the write command provided from thehost 6310 in the SSDs 6300, and output data corresponding to the writecommand to the selected SSDs 6300. Furthermore, when the RAID controllerperforms a read command in response to a read command provided from thehost 6310, the RAID controller may select one or more memory systems orSSDs 6300 according to a plurality of RAID levels, that is, RAID levelinformation of the read command provided from the host 6310 in the SSDs6300, and provide data read from the selected SSDs 6300 to the host6310.

FIG. 12 is a diagram schematically illustrating another example of thedata processing system including the memory system in accordance with anembodiment. FIG. 12 schematically illustrates an embedded Multi-MediaCard (eMMC) to which the memory system may be applied.

Referring to FIG. 12, the eMMC 6400 may include a controller 6430 and amemory device 6440 embodied by one or more NAND flash memories. Thecontroller 6430 may correspond to the controller 130 in the memorysystem 110 of FIG. 1, and the memory device 6440 may correspond to thememory device 150 in the memory system 110 of FIG. 1.

More specifically, the controller 6430 may be connected to the memorydevice 6440 through a plurality of channels. The controller 6430 mayinclude one or more cores 6432, a host interface 6431 and a memoryinterface, for example, a NAND interface 6433.

The core 6432 may control overall operations of the eMMC 6400, the hostinterface 6431 may provide an interface function between the controller6430 and the host 6410, and the NAND interface 6433 may provide aninterface function between the memory device 6440 and the controller6430. For example, the host interface 6431 may serve as a parallelinterface, for example, MMC interface as described with reference toFIG. 1. Furthermore, the host interface 6431 may serve as a serialinterface, for example, UHS ((Ultra High Speed)-I/UHS-II) interface.

FIGS. 13 to 16 are diagrams schematically illustrating other examples ofthe data processing system including the memory system in accordancewith one or more embodiments. FIGS. 12 to 15 schematically illustrateUFS (Universal Flash Storage) systems to which the memory system may beapplied.

Referring to FIGS. 13 to 16, the UFS systems 6500, 6600, 6700 and 6800may include hosts 6510, 6610, 6710 and 6810, UFS devices 6520, 6620,6720 and 6820 and UFS cards 6530, 6630, 6730 and 6830, respectively. Thehosts 6510, 6610, 6710 and 6810 may serve as application processors ofwired/wireless electronic devices or particularly mobile electronicdevices, the UFS devices 6520, 6620, 6720 and 6820 may serve as embeddedUFS devices, and the UFS cards 6530, 6630, 6730 and 6830 may serve asexternal embedded UFS devices or removable UFS cards.

The hosts 6510, 6610, 6710 and 6810, the UFS devices 6520, 6620, 6720and 6820 and the UFS cards 6530, 6630, 6730 and 6830 in the respectiveUFS systems 6500, 6600, 6700 and 6800 may communicate with externaldevices, for example, wired/wireless electronic devices or particularlymobile electronic devices through UFS protocols, and the UFS devices6520, 6620, 6720 and 6820 and the UFS cards 6530, 6630, 6730 and 6830may be embodied by the memory system 110 illustrated in FIG. 1. Forexample, in the UFS systems 6500, 6600, 6700 and 6800, the UFS devices6520, 6620, 6720 and 6820 may be embodied in the form of the dataprocessing system 6200, the SSD 6300 or the eMMC 6400 described withreference to FIGS. 10 to 12, and the UFS cards 6530, 6630, 6730 and 6830may be embodied in the form of the memory card system 6100 describedwith reference to FIG. 9.

Furthermore, in the UFS systems 6500, 6600, 6700 and 6800, the hosts6510, 6610, 6710 and 6810, the UFS devices 6520, 6620, 6720 and 6820 andthe UFS cards 6530, 6630, 6730 and 6830 may communicate with each otherthrough an UFS interface, for example, MIPI M-PHY and MIPI UniPro(Unified Protocol) in MIPI (Mobile Industry Processor Interface).Furthermore, the UFS devices 6520, 6620, 6720 and 6820 and the UFS cards6530, 6630, 6730 and 6830 may communicate with each other throughvarious protocols other than the UFS protocol, for example, UFDs, MMC,SD, mini-SD, and micro-SD.

In the UFS system 6500 illustrated in FIG. 13, each of the host 6510,the UFS device 6520 and the UFS card 6530 may include UniPro. The host6510 may perform a switching operation in order to communicate with theUFS device 6520 and the UFS card 6530. In particular, the host 6510 maycommunicate with the UFS device 6520 or the UFS card 6530 through linklayer switching, for example, L3 switching at the UniPro. At this time,the UFS device 6520 and the UFS card 6530 may communicate with eachother through link layer switching at the UniPro of the host 6510. In anembodiment, the configuration in which one UFS device 6520 and one UFScard 6530 are connected to the host 6510 has been exemplified forconvenience of description. However, a plurality of UFS devices and UFScards may be connected in parallel or in the form of a star to the host6410, and a plurality of UFS cards may be connected in parallel or inthe form of a star to the UFS device 6520 or connected in series or inthe form of a chain to the UFS device 6520.

In the UFS system 6600 illustrated in FIG. 14, each of the host 6610,the UFS device 6620 and the UFS card 6630 may include UniPro, and thehost 6610 may communicate with the UFS device 6620 or the UFS card 6630through a switching module 6640 performing a switching operation, forexample, through the switching module 6640 which performs link layerswitching at the UniPro, for example, L3 switching. The UFS device 6620and the UFS card 6630 may communicate with each other through link layerswitching of the switching module 6640 at UniPro. In an embodiment, theconfiguration in which one UFS device 6620 and one UFS card 6630 areconnected to the switching module 6640 has been exemplified forconvenience of description. However, a plurality of UFS devices and UFScards may be connected in parallel or in the form of a star to theswitching module 6640, and a plurality of UFS cards may be connected inseries or in the form of a chain to the UFS device 6620.

In the UFS system 6700 illustrated in FIG. 15, each of the host 6710,the UFS device 6720 and the UFS card 6730 may include UniPro, and thehost 6710 may communicate with the UFS device 6720 or the UFS card 6730through a switching module 6740 performing a switching operation, forexample, through the switching module 6740 which performs link layerswitching at the UniPro, for example, L3 switching. At this time, theUFS device 6720 and the UFS card 6730 may communicate with each otherthrough link layer is switching of the switching module 6740 at theUniPro, and the switching module 6740 may be integrated as one modulewith the UFS device 6720 inside or outside the UFS device 6720. In anembodiment, the configuration in which one UFS device 6720 and one UFScard 6730 are connected to the switching module 6740 has beenexemplified for convenience of description. However, a plurality ofmodules each including the switching module 6740 and the UFS device 6720may be connected in parallel or in the form of a star to the host 6710or connected in series or in the form of a chain to each other.Furthermore, a plurality of UFS cards may be connected in parallel or inthe form of a star to the UFS device 6720.

In the UFS system 6800 illustrated in FIG. 16, each of the host 6810,the UFS device 6820 and the UFS card 6830 may include M-PHY and UniPro.The UFS device 6820 may perform a switching operation in order tocommunicate with the host 6810 and the UFS card 6830. In particular, theUFS device 6820 may communicate with the host 6810 or the UFS card 6830through a switching operation between the M-PHY and UniPro module forcommunication with the host 6810 and the M-PHY and UniPro module forcommunication with the UFS card 6830, for example, through a target ID(Identifier) switching operation. At this time, the host 6810 and theUFS card 6830 may communicate with each other through target IDswitching between the M-PHY and UniPro modules of the UFS device 6820.In an embodiment, the configuration in which one UFS device 6820 isconnected to the host 6810 and one UFS card 6830 is connected to the UFSdevice 6820 has been exemplified for convenience of description.However, a plurality of UFS devices may be connected in parallel or inthe form of a star to the host 6810, or connected in series or in theform of a chain to the host 6810, and a plurality of UFS cards may beconnected in parallel or in the form of a star to the UFS device 6820,or connected in series or in the form of a chain to the UFS device 6820.

FIG. 17 is a diagram schematically illustrating another example of thedata processing system including the memory system in accordance with anembodiment. FIG. 17 is a diagram schematically illustrating a usersystem to which the memory system may be applied.

Referring to FIG. 17, the user system 6900 may include an applicationprocessor 6930, a memory module 6920, a network module 6940, a storagemodule 6950 and a user interface 6910.

More specifically, the application processor 6930 may drive componentsincluded in the user system 6900, for example, an OS, and includecontrollers, interfaces and a graphic engine which control thecomponents included in the user system 6900. The application processor6930 may be provided as System-on-Chip (SoC).

The memory module 6920 may be used as a main memory, work memory, buffermemory or cache memory of the user system 6900. The memory module 6920may include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM,DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM or LPDDR3 SDRAM or a nonvolatileRAM such as PRAM, ReRAM, MRAM or FRAM. For example, the applicationprocessor 6930 and the memory module 6920 may be packaged and mounted,based on POP (Package on Package).

The network module 6940 may communicate with external devices. Forexample, the network module 6940 may not only support wiredcommunication, but also support various wireless communication protocolssuch as code division multiple access (CDMA), global system for mobilecommunication (GSM), wideband CDMA (WCDMA), CDMA-2000, time divisionmultiple access (TDMA), long term evolution (LTE), worldwideinteroperability for microwave access (Wimax), wireless local areanetwork (WLAN), ultra-wideband (UWB), Bluetooth, wireless display(WI-DI), thereby communicating with wired/wireless electronic devices orparticularly mobile electronic devices. Therefore, the memory system andthe data processing system, in accordance with an embodiment of thepresent invention, can be applied to wired/wireless electronic devices.The network module 6940 may be included in the application processor6930.

The storage module 6950 may store data, for example, data received fromthe application processor 6930, and then may transmit the stored data tothe application processor 6930. The storage module 6950 may be embodiedby a nonvolatile semiconductor memory device such as a phase-change RAM(PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash,NOR flash and 3D NAND flash, and provided as a removable storage mediumsuch as a memory card or external drive of the user system 6900. Thestorage module 6950 may correspond to the memory system 110 describedwith reference to FIG. 1. Furthermore, the storage module 6950 may beembodied as an SSD, eMMC and UFS as described above with reference toFIGS. 11 to 16.

The user interface 6910 may include interfaces for inputting data orcommands to the application processor 6930 or outputting data to anexternal device. For example, the user interface 6910 may include userinput interfaces such as a keyboard, a keypad, a button, a touch panel,a touch screen, a touch pad, a touch ball, a camera, a microphone, agyroscope sensor, a vibration sensor and a piezoelectric element, anduser output interfaces such as a liquid crystal display (LCD), anorganic light emitting diode (OLED) display device, an active matrixOLED (AMOLED) display device, an LED, a speaker and a motor.

Furthermore, when the memory system 110 of FIG. 1 is applied to a mobileelectronic device of the user system 6900, the application processor6930 may control overall operations of the mobile electronic device, andthe network module 6940 may serve as a communication module forcontrolling wired/wireless communication with an external device. Theuser interface 6910 may display data processed by the processor 6930 ona display/touch module of the mobile electronic device, or support afunction of receiving data from the touch panel.

According to embodiments of the present invention, a memory system andan operating method of the memory system are capable of processing datawith a memory device quickly and stably by minimizing the complexity andperformance deterioration of the memory system and maximizing theutility efficiency of the memory device.

While the present invention has been described with respect to specificembodiments, it will be apparent to those skilled in the art in light ofthis disclosure that various changes and modifications may be madewithout departing from the spirit and scope of the invention as definedin the following claims.

What is claimed is:
 1. A memory system, comprising: a memory device thatincludes a plurality of memory blocks, each of which includes aplurality of pages that store data; and a controller suitable forperforming command operations corresponding to a plurality of commandsreceived from a host on the plurality of memory blocks, applying passvoltages to a dummy region of the memory device when the commandoperations are performed, detecting first parameters for the pluralityof memory blocks based on the applied pass voltages, and copying andstoring data stored in first memory blocks in second memory blocks,among the plurality of memory blocks, based on the first parameters. 2.The memory system of claim 1, wherein the dummy region includes a dummyword line or a dummy page which is set in each of the memory blocks, andwherein the controller applies the pass voltages to each dummy word lineor dummy page.
 3. The memory system of claim 2, wherein the passvoltages have a maximum level that is set based on voltage levelsapplied to each of the plurality of memory blocks when the commandoperations are performed.
 4. The memory system of claim 2, wherein thefirst parameters are voltage offsets or voltage distribution offsetscorresponding to the pass voltages applied to the dummy word line or thedummy page of each of the plurality of memory blocks.
 5. The memorysystem of claim 2, wherein the controller detects second parameters foreach of the plurality of memory blocks corresponding to performance ofthe command operations.
 6. The memory system of claim 5, wherein thesecond parameters are command operation counts corresponding to theperformance of the command operations in each of the plurality of memoryblocks.
 7. The memory system of claim 5, wherein the controller adjuststhe second parameters, and subsequently selects the first memory blocksin accordance with the adjusted second parameters.
 8. The memory systemof claim 2, wherein the dummy word line in each of the plurality ofmemory blocks is set as a region having a first bit in a first word lineor to a word line previous to the first word line, among a plurality ofword lines in each of the plurality of memory blocks.
 9. The memorysystem of claim 2, wherein the dummy page in each of the plurality ofmemory blocks is set as a region having a first bit in a first page orto a page previous to the first page, among a plurality of pages in eachof the plurality of memory blocks.
 10. The memory system of claim 1,wherein the dummy region includes a group of a plurality of word linesor a plurality of pages in each of the plurality of memory blocks, andwherein the controller applies the pass voltages to each group.
 11. Anoperating method of a memory system, comprising: receiving a pluralityof commands from a host for a memory device that includes a plurality ofmemory blocks, each of which includes a plurality of pages that storedata; performing command operations corresponding to the commands on theplurality of memory blocks; applying pass voltages to a dummy region ofthe memory device when the command operations are performed; detectingfirst parameters for the plurality of memory blocks based on the appliedpass voltages; and copying and storing data stored in first memoryblocks in second memory blocks, among the plurality of memory blocks,based on the first parameters.
 12. The operating method of claim 11,wherein the dummy region includes a dummy word line or a dummy pagewhich is set in each of the plurality of memory blocks, and wherein theapplying operation comprises applying the pass voltages to each dummyword line or dummy page.
 13. The operating method of claim 12, whereinthe pass voltages have a maximum level that is set based on voltagelevels applied to each of the plurality of memory blocks when thecommand operations are performed.
 14. The operating method of claim 12,wherein the first parameters are voltage offsets or voltage distributionoffsets corresponding to the pass voltages applied to the dummy wordline or the dummy page of each of the plurality of memory blocks. 15.The operating method of claim 12, further comprising: detecting secondparameters for each of the plurality of memory blocks corresponding toperformance of the command operations.
 16. The operating method of claim15, wherein the second parameters are command operation countscorresponding to the performance of the command operations in each ofthe plurality of memory blocks.
 17. The operating method of claim 15,wherein the storing of the data stored in first memory blocks in secondmemory blocks includes: adjusting the second parameters; and selectingthe first memory blocks in accordance with the adjusted secondparameters.
 18. The operating method of claim 12, wherein the dummy wordline each of the plurality of memory blocks is set as a region having afirst bit in a first word line or to a word line previous to the firstword line, among a plurality of word lines in each of the plurality ofmemory blocks.
 19. The operating method of claim 12, wherein the dummypage in each of the plurality of memory blocks is set as a region havinga first bit in a first page or to a page previous to the first page,among a plurality of pages in each of the plurality of memory blocks.20. The operating method of claim 11, wherein the dummy region includesa group of a plurality of word lines or a plurality of pages in each ofthe plurality of memory blocks, and wherein the applying operationcomprises applying the pass voltages to each group.